View TC7109CKW_7485926.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2002-2012 microchip technology inc. ds21456d-page 1 tc7109/a features: ? zero integrator cycle for fast recovery from input overloads ? eliminates cross-talk in multiplexed systems ? 12-bit plus sign integrating a/d converter with over range indication ? sign magnitude coding format ? true differential signal input and differential reference input ? low noise: 15 ? v p-p typ. ? input current: 1pa typ. ? no zero adjustment needed ? ttl compatible, byte organized tri-state outputs ? uart handshake mode for simple serial data transmissions device selection table *the ?a? version has a higher i out on the digital lines. general description: the tc7109a is a 12-bit plus sign, cmos low power analog-to-digital converter (adc). only eight passive components and a crystal are required to form a complete dual slope integrating adc. the improved v oh source current and other tc7109a features make it an attractive per-channel alternative to analog multiplexing for many data acquisition applica- tions. these features include typical input bias current of 1pa, drift of less than 1 ? v/c, input noise typically 15 ? v p-p , and auto-zero. true differential input and ref- erence allow measurement of bridge type transducers, such as load cells, strain gauges and temperature transducers. the tc7109a provides a versatile digital interface. in the direct mode, chip select and high /low byte enable control parallel bus interface. in the handshake mode, the tc7109a will operate with industry standard uarts in controlling serial data transmission ? ideal for remote data logging. control and monitoring of conver- sion timing is provided by the run/hold input and status output. for applications requiring more resolution, see the tc500, 15-bit plus sign adc data sheet. the tc7109a has improved over range recovery performance and higher output drive capability than the original tc7109. all new (or existing) designs should specify the tc7109a wherever possible. part number (tc7109x)* package temperature range TC7109CKW 44-pin pqfp 0c to +70c tc7109clw 44-pin plcc 0c to +70c tc7109cpl 40-pin pdip 0c to +70c tc7109ijl 40-pin cerdip -25c to +85c 12-bit ? a-compatible analog-to-digital converters
tc7109/a ds21456d-page 2 ? 2002-2012 microchip technology inc. package type nc = no internal connection tc7109a tc7109 1 2 3 4 5 6 7 8 9 10 11 12 status 13 14 15 16 17 18 19 20 pol or test lben hben ce/load ref out in hi in lo common v+ send run/hold buff osc out osc sel osc in mode 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 gnd osc out v- buff az int ref in+ ref cap+ ref cap- ref in- b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 27 28 29 30 31 32 33 7 4 3 2 1 int in hi 12 13 14 15 17 18 buff osc out az nc buff 44 43 42 41 39 38 40 gnd 16 37 36 35 34 19 20 21 22 26 8 ref out 25 9 24 10 send 23 11 nc 5 6 b 1 tc7109ackw TC7109CKW 44-pin pqfp 44-pin plcc 40-pin pdip/cerdip run/hold v- common in lo ref in+ ref cap+ ref cap- ref in- v+ status pol or b 9 b 11 b 10 b 8 b 7 nc b 6 b 5 b 4 b 3 b 2 osc sel osc out osc in mode nc ce/load hben lben test b 12 33 34 35 36 37 38 39 13 10 9 8 7 int in hi 18 19 20 21 23 24 buff osc out az nc buff 6543 144 2 gnd 22 43 42 41 40 25 26 27 28 32 14 ref out 31 15 30 16 send 29 17 nc 11 12 b 1 tc7109aclw tc7109clw run/hold v- common in lo ref in+ ref cap+ ref cap- ref in- v+ status pol or b 9 b 11 b 10 b 8 b 7 nc b 6 b 5 b 4 b 3 b 2 osc sel osc out osc in mode nc ce/load hben lben test b 12
? 2002-2012 microchip technology inc. ds21456d-page 3 tc7109/a typical application input high az buff c az int buffer integrator az zi az zi de (+) az int az comparator comp out 35 31 30 c ref az de () zi 33 34 common input low int 37 36 ref in+ de (?) de (?) de (+) r int c int 38 39 ref cap- ref cap+ zi 6.2v 10ma 28 40 v+ v- 29 ref out 17 3 4 5 6 7 8 9 10 11 12 13 14 22622 23 24 25 21 to analog section comp out az int de () zi conversion control logic oscillator and clock circuitry handshake logic 15 16 27 18 19 20 lben hben ce/load 1 gnd 14 latches 12-bit counter 16 three-state outputs send mode buff osc out osc sel osc out osc in run/ hold status pol or test high order byte inputs low order byte inputs tc7109a ref in- b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 latch clock 32 + + ? ? + ?
tc7109/a ds21456d-page 4 ? 2002-2012 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings* positive supply voltage (gnd to v+) ..................+6.2v negative supply voltage (gnd to v-) .....................-9v analog input voltage (low to high) (note 1) .... v+ to v- reference input voltage: (low to high) (note 1) ............................. v+ to v- digital input voltage: (pins 2-27) (note 2) ...........................gnd ? 0.3v power dissipation , t a < 70c (note 3) cerdip ......................................................2.29w plastic dip ..................................................1.23w plcc ..........................................................1.23w pqfp ..........................................................1.00w operating temperature range plastic package (c) ......................... 0c to +70c ceramic package (i) .....................-25c to +85c storage temperature range ..............-65c to +150c *stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. tc7109/tc7109a electrical specifications electrical characteristics: all parameters with v+ = +5v, v- = -5v, gnd = 0v, t a = +25c, unless otherwise indicated. symbol parameter min typ max unit test conditions analog overload recovery time (tc7109a) ? 0 1 measurement cycle zero input reading -0000 8 0000 8 +0000 8 octal reading v in = 0v; full scale = 409.6mv ratio metric reading 3777 8 3777 8 4000 8 4000 8 octal reading v in = v ref v ref = 204.8mv nl non-linearity (max deviation from best straight line fit) -1 0.2 +1 count full scale = 409.6mv to 2.048v over full operating temperature range rollover error (difference in reading for equal positive and inputs near (full scale) -1 0.02 +1 count full scale = 409.6mv to 2.048v over full operating temperature range cmrr input common mode rejection ratio ?50 ? ? v/v v cm 1v, v in = 0v full scale = 409.6mv v cmr common mode voltage range v- +1.5 ? v+ -1.5 v input high, input low and common pins e n noise (p-p value not exceeded 95% of time) ?15 ? ? vv in = 0v, full scale = 409.6mv i in leakage current at input ? 1 10 pa v in , all packages: +25c ? 20 100 pa c device: 0c ? t a ? +70c ? 100 250 pa i device: -25c ? t a ? +85c tc zs zero reading drift ? 0.2 1 ? v/c v in = 0v note 1: input voltages may exceed supply voltages if input current is limited to 100 ? a. 2: connecting any digital inputs or outputs to voltages greater than v+ or less than gnd may cause destructive device latch-up. therefore, it is recommended that inputs from sources other than the same power supply should not be applied to the tc7109a before its power supply is established. in multiple supply systems, the supply to the device should be activated first. 3: this limit refers to that of the package and will not occur during normal operation.
? 2002-2012 microchip technology inc. ds21456d-page 5 tc7109/a tc fs scale factor temperature coefficient ? 1 5 ? v/c v in = 408.9mv = >7770 8 reading, ext ref = 0ppm/c i + supply current (v+ to gnd) ? 700 1500 ? av in = 0v, crystal oscillator 3.58mhz test circuit i s supply current (v+ to v-) ? 700 1500 ? a pins 2-21, 25, 26, 27, 29 open v ref reference out voltage -2.4 -2.8 -3.2 v referenced to v+, 25k ? between v+ and ref out tc ref ref out temperature coefficient ? 80 ? ppm/c 25k ? between v+ and ref out 0c ?? t a ? +70c digital v oh output high voltage i out = 700 ? a 3.5 4.3 ? v tc7109: i out = 100 ? a pins 3 -16, 18, 19, 20 tc7109a: i out = 700 ? a v ol output low voltage ? 0.2 0.4 ? ai out = 1.6ma output leakage current ? 0.01 1 ? a pins 3 -16 high-impedance control i/o pull-up current ? 5 ? ? f pins 18, 19, 20 v out = v+ ? 3v mode input at gnd control i/o loading ? ? 50 pf hben , pin 19; lben , pin 18 v ih input high voltage 2.5 ? ? v pins 18 -21, 26, 27 referenced to gnd v il input low voltage ? ? 1 v pins 18-21, 26, 27 referenced to gnd input pull-up current ? ? 5 25 ? ? ? a ? a pins 26, 27; v out = v+ ? 3v pins 17, 24; v out = v+ ? 3v input pull-down current ? 1 ? ? a pins 21, v out = gnd = +3v oscillator output current, high ? 1 ? ma v out ? 2.5v oscillator output current, low ? 1.5 ? ma v out ? 2.5v buffered oscillator output current high ? 2 ? ma v out ? 2.5v buffered oscillator output current low ? 5 ? ma v out ? 2.5v t w mode input pulse width 60 ? ? nsec handling precautions: these devices are cmos and must be handled correctly to prevent damage. package and store only in conductive foam, antistatic tubes, or other conducting material. use proper antistatic handling pro- cedures. do not connect in circuits under ?power-on? conditions, as high transients may cause permanent damage. tc7109/tc7109a electrical specifications (continued) electrical characteristics: all parameters with v+ = +5v, v- = -5v, gnd = 0v, t a = +25c, unless otherwise indicated. symbol parameter min typ max unit test conditions note 1: input voltages may exceed supply voltages if input current is limited to 100 ? a. 2: connecting any digital inputs or outputs to voltages greater than v+ or less than gnd may cause destructive device latch-up. therefore, it is recommended that inputs from s ources other than the same power supply should not be applied to the tc7109a before its power supply is established. in mu ltiple supply systems, the supply to the device should be activated first. 3: this limit refers to that of the package and will not occur during normal operation.
tc7109/a ds21456d-page 6 ? 2002-2012 microchip technology inc. 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table pin number (40-pin pdip) symbol description 1 gnd digital ground, 0v, ground return for all digital logic. 2 status output high during integrate and de-int egrate until data is latched. output low when analog section is in auto-zero or zero integrator configuration. 3 pol polarity ? high for positive input. 4 or over range ? high if over ranged (three-state data bit). 5b 12 bit 12 (most significant bit) (three-state data bit). 6b 11 bit 11 (three-state data bit). 7b 10 bit 10 (three-state data bit). 8b 9 bit 9 (three-state data bit). 9b 8 bit 8 (three-state data bit). 10 b 7 bit 7 (three-state data bit). 11 b 6 bit 6 (three-state data bit). 12 b 5 bit 5 (three-state data bit). 13 b 4 bit 4 (three-state data bit). 14 b 3 bit 3 (three-state data bit). 15 b 2 bit 2 (three-state data bit). 16 b 1 bit 1 (least significant bit) (three-state data bit). 17 test input high ? normal operation. input low ? forces all bit outputs high. note: this input is used for test purposes only. 18 lben low byte enable ? with mode (pin 21) low, and ce /load (pin 20) low, taking this pin low activates low order byte outputs, b 1 ?b 8 . with mode (pin 21) high, this pin serves as low byte flag output used in handshake mo de. (see figure 3-7, figure , and figure 3-9.) 19 hben high byte enable ? with mode (pin 21) low, and ce /load (pin 20) low, taking this pin low activates high order byte outputs, b 9 ?b 12 , pol, or. with mode (pin 21) high, this pin serves as high byte flag output used in handshake mode. see figur es 3-7, 3-8, and 3-9. 20 ce /load chip enable/load ? with mode (pin 21) low, ce/load serves as a master output enable. when high, b 1 ?b 12 , pol, or outputs are disabled. when mode (pin 21) is high, a load strobe is used in handshake mode. (see figure 3-7, figure , and figure 3-9.) 21 mode input low ? direct output mode where ce /load (pin 20), hben (pin 19), and lben (pin 18) act as inputs directly controlling byte outputs. input pulsed high - causes immediate entry into handshake mode and output of data as in figure 3-9. input high ? enables ce /load (pin 20), hben (pin 19), and lben (pin 18) as outputs, handshake mode will be entered and data output as in figure 3-7 and figure 3-9 at conversions completion. 22 osc in oscillator input. 23 osc out oscillator output. 24 osc sel oscillator select ? input high configures osc in, osc out, buff osc out as rc oscillator ? clock will be same phase and duty cycle as buff osc out. input low configures osc in, osc out for crystal oscillator - clock frequency will be 1/58 of frequency at buff osc out. 25 buff osc out buffered oscillator output. 26 run/hold input high ? conversions continuous ly performed every 8192 clock pulses. input low ? conversion in progress complet ed; converter will stop in auto-zero seven counts before integrate. 27 send input - used in handshake mode to indicate ability of an external device to accept data. connect to v+ if not used. 28 v- analog negative supply ? nominally -5v with respect to gnd (pin 1). 29 ref out reference voltage output ? nominally 2.8v down from v+ (pin 40).
? 2002-2012 microchip technology inc. ds21456d-page 7 tc7109/a note: all digital levels are positive true. 30 buff buffer amplifier output. 31 az auto-zero node ? inside foil of c az . 32 int integrator output ? outside foil of c int . 33 common analog common ? system is auto-zeroed to common. 34 in lo differential input low side. 35 in hi differential input high side. 36 ref in+ differential reference input positive. 37 ref cap+ reference capacitor positive. 38 ref cap- reference capacitor negative. 39 ref in- differential reference input negative. 40 v+ positive supply voltage ? nominally +5v with respect to gnd (pin 1). table 2-1: pin function table (continued) pin number (40-pin pdip) symbol description
tc7109/a ds21456d-page 8 ? 2002-2012 microchip technology inc. 3.0 detailed description (all pin designations refer to 40-pin dip.) 3.1 analog section the typical application diagram on page 3 shows a block diagram of the analog section of the tc7109a. the circuit will perform conversions at a rate deter- mined by the clock frequency (8192 clock periods per cycle), when the run/hold input is left open or connected to v+. each measurement cycle is divided into four phases, as shown in figure 3-1. they are: (1) auto-zero (az), (2) signal integrate (int), (3) reference de-integrate (de), and (4) zero integrator (zi). 3.1.1 auto-zero phase the buffer and the integrator inputs are disconnected from input high and input low and connected to analog common. the reference capacitor is charged to the ref- erence voltage. a feedback loop is closed around the system to charge the auto-zero capacitor, c az , to com- pensate for offset voltage in the buffer amplifier, inte- grator, and comparator. since the comparator is included in the loop, the az accuracy is limited only by the noise of the system. the offset referred to the input is less than 10 ? v. 3.1.2 signal integrate phase the buffer and integrator inputs are removed from com- mon and connected to input high and input low. the auto-zero loop is opened. the auto-zero capacitor is placed in series in the loop to provide an equal and opposite compensating offset voltage. the differential voltage between input high and input low is integrated for a fixed time of 2048 clock periods. at the end of this phase, the polarity of the integrated signal is determined. if the input signal has no return to the converter?s power supply, input low can be tied to analog common to establish the correct common mode voltage. 3.1.3 de-integrate phase input high is connected across the previously charged reference capacitor and input low is internally connected to analog common. circuitry within the chip ensures the capacitor will be connected with the correct polarity to cause the integrator output to return to the zero crossing (established by auto-zero), with a fixed slope. the time, represented by the number of clock periods counted for the output to return to zero, is proportional to the input signal. 3.1.4 zero integrator phase the zi phase only occurs when an input over range condition exists. the function of the zi phase is to eliminate residual charge on the integrator capacitor after an over range measurement. unless removed, the residual charge will be transferred to the auto-zero capacitor and cause an error in the succeeding conversion. the zi phase virtually eliminates hysteresis, or ?cross- talk? in multiplexed systems. an over range input on one channel will not cause an error on the next channel measured. this feature is especially useful in thermo- couple measurements, where unused (or broken thermocouple) inputs are pulled to the positive supply rail. during zi, the reference capacitor is charged to the ref- erence voltage. the signal inputs are disconnected from the buffer and integrator. the comparator output is connected to the buffer input, causing the integrator output to be driven rapidly to 0v (figure 3-1). the zi phase only occurs following an over range and lasts for a maximum of 1024 clock periods. 3.1.5 differential input the tc7109a has been optimized for operation with analog common near digital ground. with +5v and -5v power supplies, a full 4v full scale integrator swing maximizes the analog section?s performance. a typical cmrr of 86db is achieved for input differen- tial voltages anywhere within the typical common mode range of 1v below the positive supply, to 1.5v above the negative supply. however, for optimum per- formance, the in hi and in lo inputs should not come within 2v of either supply rail. since the integrator also swings with the common mode voltage, care must be exercised to ensure the integrator output does not sat- urate. a worst-case condition is near a full scale nega- tive differential input voltage with a large positive common mode voltage. the negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode volt- age. in such cases, the integrator swing can be reduced to less than the recommended 4v full scale value, with some loss of accuracy. the integrator output can swing to within 0.3v of either supply without loss of linearity.
? 2002-2012 microchip technology inc. ds21456d-page 9 tc7109/a 3.1.6 differential reference the reference voltage can be generated anywhere within the power supply voltage of the converter. roll- over voltage is the main source of common mode error, caused by the reference capacitor losing or gain- ing charge, due to stray capacity on its nodes. with a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called upon to de-integrate a positive signal and lose charge (decrease voltage) when called upon to de-integrate a negative input signal. this difference in reference for (+) or (?) input voltages will cause a rollover error. this error can be held to less than 0.5 count, worst-case, by using a large reference capacitor in comparison to the stray capacitance. to minimize rollover error from these sources, keep the reference common mode voltage near or at analog common. 3.2 digital section the digital section is shown in figure 3-2 and includes the clock oscillator and scaling circuit, a 12-bit binary counter with output latches and ttl compatible three- state output drivers, uart handshake logic, polarity, over range, and control logic. logic levels are referred to as low or high. inputs driven from ttl gates should have 3k ? to 5k ? pull-up resistors added for maximum noise immunity. for minimum power consumption, all inputs should swing from gnd (low) to v+ (high). 3.2.1 status output during a conversion cycle, the status output goes high at the beginning of signal integrate and goes low one- half clock period after new data from the conversion has been stored in the output latches (see figure 3-1). the signal may be used as a ?data valid? flag to drive interrupts, or for monitoring the status of the converter. (data will not change while status is low.) 3.2.2 mode input the output mode of the converter is controlled by the mode input. the converter is in its ?direct? output mode, when the mode input is low or left open. the output data is directly accessible under the control of the chip and byte enable inputs (this input is provided with a pull-down resistor to ensure a low level when the pin is left open). when the mode input is pulsed high, the converter enters the uart handshake mode and outputs the data in 2 bytes, then returns to ?direct? mode. when the mode input is kept high, the converter will output data in the handshake mode at the end of every conversion cycle. with mode = 0 (direct bus transfer), the send input should be tied to v+. (see ?handshake mode?.) 3.2.3 run/hold input with the run/hold input high, or open, the circuit operates normally as a dual slope adc, as shown in figure 3-1. conversion cycles operate continuously with the output latches updated after zero crossing in the de-integrate mode. an internal pull-up resistor is provided to ensure a high level with an open input. the run/hold input may be used to shorten conver- sion time. if run/hold goes low any time after zero crossing in the de-integrate mode, the circuit will jump to auto-zero and eliminate that portion of time normally spent in de-integrate. if run/hold stays or goes low, the conversion will complete with minimum time in de-integrate. it will stay in auto-zero for the minimum time and wait in auto-zero for a high at the run/hold input. as shown in figure 3-3, the status output will go high, 7 clock peri- ods after run/hold is changed to high, and the converter will begin the integrate phase of the next conversion. the run/hold input allows controlled conversion interface. the converter may be held at idle in auto- zero with run/hold low. the conversion is started when run/hold goes high, and the new data is valid when the status output goes low (or is trans- ferred to the uart; see ?handshake mode?). run/ hold may now go low, terminating de-integrate and ensuring a minimum auto-zero time before stopping to wait for the next conversion. conversion time can be minimized by ensuring run/hold goes low during de-integrate, after zero crossing, and goes high after the hold point is reached. the required activity on the run/hold input can be provided by connecting it to the buffered oscillator output. in this mode, the input value measured determines the conversion time.
tc7109/a ds21456d-page 10 ? 2002-2012 microchip technology inc. figure 3-1: conversion timing (run/hold ) pin high figure 3-2: digital section internal clock integrator output for normal input integrator saturates internal latch integrator output for over range input no zero crossing zi az zero integrator phase forces integrator output to 0v zero crossing occurs zero crossing detected int phase ii status output az phase i de phase iii az fixed 2048 counts 2048 counts min. 4096 counts max number of counts to zero crossing proportional to v in after zero crossing, analog section will be in auto-zero configuration test 17 pol 3 or 4 b 12 5 b 11 6 b 10 7 b 9 8 b 8 9 b 7 10 b 6 11 b 5 12 b 4 13 b 3 14 2262223242521 status run/ hold osc in osc out osc sel buff osc out mode to analog section comp out az int de () zi conversion control logic oscillator and clock circuitry high order byte outputs low order byte outputs handshake logic b 2 15 b 1 16 27 send 18 19 20 lben hben ce/load 1 gnd 14 latches 12-bit counter 14 three-state outputs latch clock
? 2002-2012 microchip technology inc. ds21456d-page 11 tc7109/a figure 3-3: tc7109a run/hold operation 3.2.4 direct mode the data outputs (bits 1 through 8, low order bytes; bits 9 through 12, polarity and over range high order bytes) are accessible under control of the byte and chip enable terminals as inputs, with the mode pin at a low level. these three inputs are all active low. internal pull-up resistors are provided for an inactive high level when left open. when chip enable is low, a byte enable input low will allow the outputs of the byte to become active. a variety of parallel data accessing techniques may be used, as shown in the ?interfacing? section. (see figure 3-4 and table 3-1.) the access of data should be synchronized with the conversion cycle by monitoring the status output. this prevents accessing data while it is being updated and eliminates the acquisition of erroneous data. figure 3-4: tc7109a direct mode output timing table 3-1: tc7109a direct mode timing requirements 3.2.5 handshake mode an alternative means of interfacing the tc7109a to digital systems is provided when the handshake out- put mode of the tc7109a becomes active in controlling the flow of data, instead of passively responding to chip and byte enable inputs. this mode allows a direct inter- face between the tc7109a and industry standard uarts with no external logic required. the tc7109a provides all the control and flag signals necessary to sequence the two bytes of data into the uart and ini- tiate their transmission in serial form when triggered into the handshake mode. the cost of designing remote data acquisition stations is reduced using serial data transmission to minimize the number of lines to the central controlling processor. integrator output internal clock determinated at zero crossing detection auto-zero phase i min 1790 counts max 2041 counts static in hold state int phase ii run/hold input is ignored until end of auto-zero phase. *note: * internal latch status output run/hold input 7 counts = high-impedance ce/load as input t cea t bea hben as input t dab t dab lben as input high byte data low byte data data valid t dac t dhc data valid data valid symbol description min typ max units t bea byte enable width 200 500 ? nsec t dab data access time from byte enable ? 150 300 nsec t dhb data hold time from byte enable ? 150 300 nsec t cea chip enable width 300 500 nsec t dac data access time from chip enable ? 200 400 nsec t dhc data hold time from chip enable ? 200 400 nsec
tc7109/a ds21456d-page 12 ? 2002-2012 microchip technology inc. the mode input controls the handshake mode. when the mode input is held high, the tc7109a enters the handshake mode after new data has been stored in the output latches at the end of every conversion per- formed (see figure 3-7 and figure ). entry into the handshake mode may be triggered on demand by the mode input. at any time during the conversion cycle, the low-to-high transition of a short pulse at the mode input will cause immediate entry into the hand- shake mode. if this pulse occurs while new data is being stored, the entry into handshake mode is delayed until the data is stable. the mode input is ignored in the handshake mode, and until the converter completes the output cycle and clears the handshake mode, data updating will be inhibited (see figure 3-9). when the mode input is high, or when the converter enters the handshake mode, the chip and byte enable inputs become ttl compatible outputs, which provide the output cycle control signals (see figure 3-7, figure and figure 3-9). the send input is used by the con- verter as an indication of the ability of the receiving device (such as a uart) to accept data in the hand- shake mode. the sequence of the output cycle with send held high is shown in figure 3-7. the hand- shake mode (internal mode high) is entered after the data latch pulse (the ce /load , lben and hben terminals are active as outputs, since mode remains high). the high level at the send input is sensed on the same high-to-low internal clock edge. on the next low-to-high internal clock edge, the high order byte (bits 9 through 12, pol, and or) outputs are enabled and the ce /load and the hben outputs assume a low level. the ce /load output remains low for one full internal clock period only; the data outputs remain active for 1-1/2 internal clock periods; and the high byte enable remains low for 2 clock periods. the ce /load output low level, or low-to-high edge, may be used as a synchronizing signal to ensure valid data, and the byte enable as an output may be used as a byte identification flag. with send remaining high, the converter completes the output cycle using ce /load and lben , while the low order byte outputs (bits 1 through 8) are activated. when both bytes are sent, the handshake mode is terminated. the typical uart interfacing timing is shown in figure . the send input is used to delay portions of the sequence, or handshake, to ensure correct data trans- fer. this timing diagram shows an industry standard hd6403 or cdp1854 cmos uart to interface to serial data channels. the send input to the tc7109a is driven by the tbre (transmitter buffer register empty) output of the uart, and the ce /load input of the tc7109a drives the tbrl (transmitter buffer register load) input to the uart. the eight transmitter buffer register inputs accept the parallel data outputs. with the uart transmitter buffer register empty, the send input will be high when the handshake mode is entered, after new data is stored. the high order byte outputs become active and the ce /load and hben inputs will go low after send is sensed. when ce / load goes high at the end of one clock period, the high order byte data is clocked into the uart transmit- ter buffer register. the uart tbre output will go low, which halts the output cycle with the hben output low, and the high order byte outputs active. when the uart has transferred the data to the transmitter regis- ter and cleared the transmitter buffer register, the tbre returns high. the high order byte outputs are disabled on the next tc7109a internal clock high-to- low edge, and one-half internal clock later, the hben output returns high. the ce /load and lben outputs go low at the same time as the low order byte outputs become active. when the ce /load returns high at the end of one clock period, the low order data is clocked into the uart transmitter buffer register, and tbre again goes low. the next tc7109a internal clock high-to-low edge will sense when tbre returns to a high, disabling the data inputs. one-half internal clock later, the handshake mode is cleared, and the ce /load , hben and lben terminals return high and stay active, if mode still remains high. handshake output sequences may be performed on demand by triggering the converter into handshake mode with a low-to-high edge on the mode input. a handshake output sequence triggered is shown in figure 3-9. the send input is low when the converter enters handshake mode. the whole output sequence is controlled by the send input, and the sequence for the first (high order) byte is similar to the sequence for the second byte. figure 3-9 also shows that the output sequence can take longer than a conversion cycle. new data will not be latched when the handshake mode is still in prog- ress and is, therefore, lost. 3.3 oscillator the oscillator may be over driven, or may be operated as an rc or crystal oscillator. the oscillator select input optimizes the internal configuration of the oscillator for rc or crystal operation. the oscil- lator select input is provided with a pull-up resis- tor. when the oscillator select input is high or left open, the oscillator is configured for rc operation. the internal clock will be the same frequency and phase as the signal at the buffered oscillator output. connect the resistor and capacitor as in figure . the circuit will oscillate at a frequency given by f = 0.45/rc. a 100k ? resistor is recommended for use- ful ranges of frequency. the capacitor value should be chosen such that 2048 clock periods are close to an integral multiple of the 60hz period for optimum 60hz line rejection.
? 2002-2012 microchip technology inc. ds21456d-page 13 tc7109/a figure 3-5: tc7109a rc oscillator with oscillator select input low, two on-chip capacitors and a feedback device are added to the oscillator. in this configuration, the oscillator will oper- ate with most crystals in the 1mhz to 5mhz range, with no external components (figure ). the oscillator select input low inserts a fixed 458 divider circuit between the buffered oscillator output and the internal clock. a 3.58mhz tv crystal gives a division ratio, providing an integration time given by: equation 3-1: figure 3-6: crystal oscillator the error is less than 1% from two 60hz periods, or 33.33msec, which will give better than 40db, 60hz rejection. the converter will operate reliably at conver- sion rates up to 30 per second, corresponding to a clock frequency of 245.8khz. when the oscillator is to be over driven, the oscilla- tor output should be left open, and the over driving signal should be applied at the oscillator input. the internal clock will be of the same duty cycle, fre- quency and phase as the input signal. when the oscillator select is at gnd, the clock will be 1/58 of the input frequency. figure 3-7: tc7109a handshake with send input held positive 23 osc out 25 buffered osc out 24 osc sel v+ or open 22 osc in r c f osc = 0.45/rc t = ( 2048 clock periods) = 33.18 msec 58 3.58 mhz 23 osc out 25 buffered osc out 24 osc sel gnd v+ 22 osc in 58 clock crystal = three-state high-impendance integrator output data invalid data valid internal clock internal latch status output mode input internal mode send input ce/load hben high byte data lben low byte data = don't care = three-state will pull-up uart norm terminates uart mode zero crossing detected zero crossing occurs send sensed send sensed mode low, not in handshake mode disables outputs ce/load, hben, lben mode high activates ce/load, hben, lben
tc7109/a ds21456d-page 14 ? 2002-2012 microchip technology inc. figure 3-8: tc7109a handshake ? typical uart interface timing figure 3-9: tc7109a handshake triggered by mode input = three-state high-impedance integrator output data valid internal clock internal latch status output mode input internal mode send input (uart tbre) ce/load output (uart tbrl) hben high byte data lben low byte data = don't care uart norm terminates uart mode zero crossing detected zero crossing occurs send sensed send sensed send sensed data valid data valid data valid terminates uart mode = three-state high-impedance internal clock internal latch status output mode input internal mode send input ce/load as output hben high byte data lben low byte data = don't care = three-state with pull-up uart norm send sensed send sensed zero crossing detected zero crossing occurs status output unchanged in uart mode latch pulse inhibited in uart mod e positive transiton causes entry into uart mode de phase iii send sensed
? 2002-2012 microchip technology inc. ds21456d-page 15 tc7109/a 3.4 test input the counter and its outputs may be tested easily. when the test input is connected to gnd, the internal clock is disabled and the counter outputs are all forced into the high state. when the input returns to the 1/2 (v+ ? gnd) voltage or to v+ and one clock is input, the counter outputs will all be clocked to the low state. the counter output latches are enabled when the test input is taken to a level halfway between v+ and gnd, allowing the counter contents to be examined any time. 3.5 component value selection the integrator output swing for full scale should be as large as possible. for example, with 5v supplies and common connected to gnd, the nominal integrator output swing at full scale is 4v. since the integrator output can go to 0.3v from either supply without signif- icantly effecting linearity, a 4v integrator output swing allows 0.7v for variations in output swing, due to com- ponent value and oscillator tolerances. with 5v sup- plies and a common mode voltage range of 1v required, the component values should be selected to provide 3v integrator output swing. noise and roll- over errors will be slightly worse than in the 4v case. for large common mode voltage ranges, the integrator output swing must be reduced further. this will increase both noise and rollover errors. to improve performance, 6v supplies may be used. 3.5.1 integrating capacitor the integrating capacitor, c int , should be selected to give the maximum integrator output voltage swing that will not saturate the integrator to within 0.3v from either supply. a 3.5v to 4v integrator output swing is nom- inal for the tc7109a, with 5v supplies and analog common connected to gnd. for 7-1/2 conversions per second (61.72khz internal clock frequency), nominal values c int and c az are 0.15 ? f and 0.33 ? f, r e sp ec - tively. these values should be changed if different clock frequencies are used to maintain the integrator output voltage swing. the value of c int is given by: equation 3-2: the integrating capacitor must have low dielectric absorption to prevent rollover errors. polypropylene capacitors give undetectable errors, at reasonable cost, up to +85c. 3.5.2 integrating resistor the integrator and buffer amplifiers have a class a out- put stage with 100 ? a of quiescent current. they supply 20 ? a of drive current with negligible non-linearity. the integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the pc board. for 2.048v full scale, a 100k ? resistor is recommended and for 409.6mv full scale, a 20k resistor is recommended. r int may be selected for other values of full scale by: equation 3-3: 3.5.3 auto-zero capacitor as the auto-zero capacitor is made large, the system noise is reduced. since the tc7109a incorporates a zero integrator cycle, the size of the auto-zero capaci- tor does not affect overload recovery. the optimal value of the auto-zero capacitor is between 2 and 4 times c int . a typical value for c az is 0.33 ? f. the inner foil of c az should be connected to pin 31 and the outer foil to the rc summing junction. the inner foil of c int should be connected to the rc summing junction and the outer foil to pin 32, for best rejection of stray pickups. 3.5.4 reference capacitor a 1 ? f capacitor is recommended for most circuits. however, where a large common mode voltage exists, a larger value is required to prevent rollover error (e.g., the reference low is not analog common), and a 409.6mv scale is used. the rollover error will be held to 0.5 count with a 10 ? f capacitor. 3.5.5 reference voltage to generate full scale output of 4096 counts, the analog input required is v in = 2v ref . for 409.6mv full scale, use a reference of 204.8mv. in many applications, where the adc is connected to a transducer, a scale factor will exist between the input voltage and the digital reading. for instance, in a measuring system, the designer might like to have a full scale reading when the voltage for the transducer is 700mv. instead of dividing the input down to 409.6mv, the designer should use the input voltage directly and select v ref = 350mv. suitable values for integrating resistor and capacitor would be 34k ? and 0.15 ? f. t h is m ak es the system slightly quieter and also avoids a divider network on the input. another advantage of this system occurs when temperature and weight measurements, with an offset or tare, are desired for non-zero input. the offset may be introduced by connecting the voltage output of the transducer between common and analog high, and the offset voltage between common and ana- log low, observing polarities carefully. in processor based systems using the tc7109a, it may be more desirable to use software and perform this type of scaling or tare subtraction digitally. ( 2048 clock period) ( 20 ? a) integrator output voltage swings c int = full scale voltage 20 ? a r int =
tc7109/a ds21456d-page 16 ? 2002-2012 microchip technology inc. 3.5.6 reference sources a major factor in the absolute accuracy of the adc is the stability of the reference voltage. the 12-bit resolu- tion of the tc7109a is one part in 4096, or 244 ppm. thus, for the on-board reference temperature coeffi- cient of 70ppm/c, a temperature difference of 3c will introduce a one-bit absolute error. where the ambient temperature is not controlled, or where high accuracy absolute measurements are being made, it is recommended that an external high quality reference be used. a reference output (pin 29) is provided, which may be used with a resistive divider to generate a suitable ref- erence voltage (20ma may be sunk without significant variation in output voltage). a pull-up bias device is pro- vided, which sources about 10 ? a. the output voltage is nominally 2.8v below v+. when using the on-board reference, ref out (pin 29) should be connected to ref in- (pin 39), and ref in+ should be connected to the wiper of a precision potentiometer between ref out and v+. the test circuit shows the circuit for a 204.8mv reference, generated by a 2k ? precision potentiometer in series with a 24k ? fixed resistor.
? 2002-2012 microchip technology inc. ds21456d-page 17 tc7109/a 4.0 interfacing 4.1 direct mode combinations of chip enable and byte enable control signals, which may be used when interfacing the tc7109a to parallel data lines, are shown in figure . the ce /load input may be tied low, allowing either byte to be controlled by its own enable (see figure (a)). figure (b) shows the hben and lben as flag inputs, and ce /load as a master enable, which could be the read strobe available from most microprocessors. figure (c) shows a configuration where the two byte enables are connected together. the ce /load is a chip enable, and the hben and lben may be used as a second chip enable, or connected to ground. the 14 data outputs will be enabled at the same time. in the direct mode, send should be tied to v+. figure shows interfacing several tc7109a?s to a bus, ganging the hben and lben signals to several converters together, and using the ce /load input to select the desired converter. figure through figure give practical circuits utilizing the parallel three-state output capabilities of the tc7109a. figure shows parallel interface to the 8748/ 49 systems via an 8255 ppi, where the tc7109a data outputs are active at all times. this interface can be used in a read-after-update sequence, as shown in figure . the data is accessed by the high-to-low transition of the status driving an interrupt to the microcontroller. the run/hold input is also used to initiate conversions under software control. direct interfacing to most microcontroller busses is easily accomplished through the three-state output of the tc7109a. figure 4-8 is a typical connection diagram. to ensure requirements for setup and hold times, minimum pulse widths, and the drive limitations on long busses are met, it is necessary to carefully consider the system timing in this type of interface. this type of interface is used when the memory peripheral address density is low, providing simple address decoding. interrupt handling can be simplified by using an interface to reduce the component count. figure 4-1: direct mode chip and byte enable combination tc7109a mode ce/load b 9 - b 12 pol, or b 1 - b 8 lben hben gnd 8 analog in 6 convert control run/hold tc7109a mode ce/load b 1 - b 12 pol, or lben hben gnd analog in convert run/hold tc7109a mode ce/load b 9 - b 12 pol, or b 1 - b 8 lben hben 8 analog in 6 convert run/hold chip select 1 gnd or chip select 2 14 byte flags gnd chip select a. b. c.
tc7109/a ds21456d-page 18 ? 2002-2012 microchip technology inc. figure 4-2: three-stating several tc7109as to a small bus figure 4-3: full time parallel interface to ? pd8748h/494 microcontrollers tc7109a mode ce/load b 9 - b 12 pol, or b 1 - b 8 lben hben gnd 8 analog in 6 run/hold +5v converter select converter select converter select tc7109a mode ce/load b 9 - b 12 pol, or b 1 - b 8 lben hben gnd 8 analog in 6 run/hold +5v tc7109a mode ce/load b 9 - b 12 pol, or b 1 - b 8 lben hben gnd 8 analog in 6 run/hold +5v byte select flags tc7109a mode ce/load b 9 - b 12 pol, or b 1 - b 8 status run/hold lben hben gnd gnd 8 6 see text pd8255a (mode 0) rd wr d7 - d0 a0 - a1 cs pa5 - pa0 pb7 - pb0 pc5 pd8748h/49h data bus control bus address bus analog in +5v
? 2002-2012 microchip technology inc. ds21456d-page 19 tc7109/a figure 4-4: full time parallel interface to ? pd8748h/494 microcontrollers figure 4-5: tc7109a handshake interface to ? pd8748h/494 microcontrollers tc7109a mode ce/load b 9 - b 12 pol, or b 1 - b 8 status run/hold lben hben gnd gnd 8 6 +5v (see text) 1mf pd8255a rd wr d7 - d0 pc6 a0 - a1 cs pa5 - pa0 pb7 - pb0 pc4 stb a pc6 intr pd8748h/49h data bus control bus address bus intr a analog in 10kw tc7109a b 9 - b 12 pol, or b 1 - b 8 ce/load send run/hold mode 8 6 pd8255a (mode 1) rd wr d7 - d0 pc a0 - a1 cs pa7 - pa0 pc4 pc5 pc6 pc7 intr pd8748h/49h data bus control bus address bus analog in stb a pc3 ibf a
tc7109/a ds21456d-page 20 ? 2002-2012 microchip technology inc. 4.2 handshake mode the handshake mode provides an interface to a wide variety of external devices. the byte enables may be used as byte identification flags, or as load enables, and external latches may be clocked by the rising edge of ce /load . a handshake interface to intel ? micropro- cessors using an 8255 ppi is shown in figure . the handshake operation with the 8255 is controlled by inverting its input buffer full (ibf) flag to drive the send input to the tc7109a, and using the ce /load to drive the 8255 strobe. the internal control register of the ppi should be set in mode 1 for the port used. if the 8255 ibf flag is low and the tc7109a is in hand- shake mode, the next word will be strobed into the port. the strobe will cause ibf to go high (send goes low), which will keep the enabled byte outputs active. the ppi will generate an interrupt which, when executed, will result in the data being read. the ibf will be reset low when the byte is read, causing the tc7109a to sequence into the next byte. the mode input to the tc7109a is connected to the control line on the ppi. the data from every conversion will be sequenced in two bytes in the system, if this output is left high, or tied high separately. (the data access must take less time than a conversion.) the output sequence can be obtained on demand if this output is made to go from low to high and the interrupt may be used to reset the mode bit. conversions may be obtained on command under soft- ware control by driving the run/hold input to the tc7109a by a bit of the 8255. another peripheral device may be serviced by the unused port of the 8255. the handshake mode is particularly useful for directly interfacing to industry standard uarts (such as intersil hd-6402), providing a means of serially transmitting converted data with minimum component count. a typical uart connection is shown in figure . in this circuit, any word received by the uart causes the uart dr (data ready) output to go high. the mode input to the tc7109a goes high, triggering the tc7109a into handshake mode. the high order byte is output to the uart and when the uart has trans- ferred the data to the transmitter register, tbre (send) goes high again, lben will go high, driving the uart drr (data ready reset), which will signal the end of the transfer of data from the tc7109a to the uart. an extension of the typical connection to several tc7109a?s with one uart is shown in figure 4-7. in this circuit, the word received by the uart (available at the rbr outputs when dr is high) is used to select which converter will handshake with the uart. up to eight tc7109a?s may interface with one uart, with no external components. up to 256 converters may be accessed on one serial line with additional components. figure 4-6: tc7109 typical uart interface 1 25 2 19 17 18 21 20 27 gnd buff osc out status hben b 1 - b 8 test lben mode ce/load send v+ 40 39 38 37 36 35 34 33 32 31 30 29 28 26 24 23 22 tc7109a clk q3 reset 1 3 4 5?12 13 14 15 16 v gnd rrd rbr1?8 pe fe oe sfd rr1 tro trc rrc epe cls1 cls2 sbs pi crl *tbr1?8 tre drr dr tbrl tbre mr 40 17 39 38 37 36 35 34 24 18 19 23 22 21 hd-640r cmos uart +5v gnd +5v gnd 25 serial input 20 serial output 15 10 11 gnd gnd +5v +5v gnd +5v -5v +5v or open gnd 3.58mhz crystal analog gnd external reference + + ? input c az 0.33 f c int 0.15 f 0.01 f 1m 1 f 6 8 3?8 9?16 b 9 - b 12 , pol, or 26?33 for lowest power consumption, tbr1-tbr8 inputs should have 100k pull-up resistors to +5v. send any word to uart to transmit latest result. r int 20k 100k 0.2v ref 1v ref cd4060b ref in- ref cap- ref cap+ ref in+ in hi in lo com int az ref out buff v- run/hold osc sel osc out osc in 8 ? *note:
? 2002-2012 microchip technology inc. ds21456d-page 21 tc7109/a figure 4-7: handshake interface for multiplexed converters figure 4-8: connection diagram tc7109a b 9 - b 12 pol, or b 1 - b 8 lben hben 8 6 analog in run/hold send mode ce/ load +5v tc7109a b 9 - b 12 pol, or b 1 - b 8 lben hben 8 6 8-bit data bus analog in run/hold send mode ce/ load +5v tc7109a b 9 - b 12 pol, or b 1 - b 8 lben hben 8 6 analog in run/hold send mode ce/ load +5v tbrl drr gnd tbre rbr1 - rbr8 sfd tbr1 - tbr8 serial output serial input 6402 cmos uart 23 40 1 17 v+ gnd test run/hold status lben hben 39 38 37 36 35 34 33 32 31 30 29 28 27 25 24 23 22 21 tc7109a 1 4 5 6 7 10 9 11 25 26 39 40 20 t0 reset ss int ea wr psen ale prog v dd t1 v cc gnd p20 - p27 2 pd8748h/49h cmos microcomputer +5v other i/o +5v gnd -5v gnd 3.58mhz crystal analog gnd external reference + + ? input c az 0.33 f r int 20k 10 k 0.2 v ref 1 v ref xtal2 xtal1 8 5 p14 - p17 p13 p12 p11 p10 db0 - db7 rd 30 29 28 27 b 9 - b 12 , pol, or b 1 - b 8 ce/load 21-24, 35-38 12-19 8 31-34 26 2 18 19 c int 0.15 f 0.01 f 1m 1 f gnd +5v +5v +5v +5v gnd 23 6 8 3-8 9-16 20 ref in- ref cap- ref cap+ ref in+ in hi hi lo com int az buff ref out v- osc sel osc out osc in send buff osc out mode 8 ?
tc7109/a ds21456d-page 22 ? 2002-2012 microchip technology inc. 5.0 integrating converter features the output of integrating adcs represents the integral, or average, of an input voltage over a fixed period of time. compared with techniques in which the input is sampled and held, the integrating converter averages the effects of noise. a second important characteristic is that time is used to quantize the answer, resulting in extremely small non-linearity errors and no missing output codes. the integrating converter also has very good rejection of frequencies whose periods are an integral multiple of the measurement period. this feature can be used to advantage in reducing line frequency noise (figure ). figure 5-1: normal mode rejection of dual slope converter as a function of frequency 30 20 10 0 0.1/t 1/t 10/t input frequency normal mode rejection plan t = measurement period
? 2002-2012 microchip technology inc. ds21456d-page 23 tc7109/a 6.0 packaging information 6.1 package marking information package marking data not available at this time. 6.2 taping form component taping orientation for 44-pin pqfp devices user direction of feed pin 1 standard reel component orientation for 713 suffix device w p package carrier width (w) pitch (p) part per full reel reel size 44-pin pqfp 24 mm 16 mm 500 13 in carrier tape, number of components per reel and reel size note: drawing does not represent total number of pins.
tc7109/a ds21456d-page 24 ? 2002-2012 microchip technology inc. .557 (14.15) .537 (13.65) .398 (10.10) .390 (9.90) .031 (0.80) typ. .018 (0.45) .012 (0.30) .398 (10.10) .390 (9.90) .010 (0.25) typ. .096 (2.45) max. .557 (14.15) .537 (13.65) .083 (2.10) .075 (1.90) .041 (1.03) .026 (0.65) 7 max. .009 (0.23) .005 (0.13) 44-pin pqfp pin 1 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2002-2012 microchip technology inc. ds21456d-page 25 tc7109/a 6.3 package dimensions dimensions: inches (mm) 2.065 (52.45) 2.027 (51.49) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .022 (0.56) .015 (0.38) .110 (2.79) .090 (2.29) .555 (14.10) .530 (13.46) .610 (15.49) .590 (14.99) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .040 (1.02) .020 (0.51) 40-pin pdip (wide) pin1 3 min. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging dimensions: inches (mm) .015 (0.38) .008 (0.20) .620 (15.75) .590 (15.00) .700 (17.78) .620 (15.75) .540 (13.72) .510 (12.95) 2.070 (52.58) 2.030 (51.56) .210 (5.33) .170 (4.32) .020 (0.51) .016 (0.41) .110 (2.79) .090 (2.29) .065 (1.65) .045 (1.14) .200 (5.08) .125 (3.18) .098 (2.49) max. .030 (0.76) min. .060 (1.52) .020 (0.51) .150 (3.81) min. 40-pin cerdip (wide) pin 1 3 min. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
tc7109/a ds21456d-page 26 ? 2002-2012 microchip technology inc. 6.3 package dimensions (continued) dimensions: inches (mm) .557 (14.15) .537 (13.65) .398 (10.10) .390 (9.90) .031 (0.80) typ. .018 (0.45) .012 (0.30) .398 (10.10) .390 (9.90) .010 (0.25) typ. .096 (2.45) max. .557 (14.15) .537 (13.65) .083 (2.10) .075 (1.90) .041 (1.03) .026 (0.65) 7 max. .009 (0.23) .005 (0.13) 44-pin pqfp pin 1 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging dimensions: inches (mm) pin 1 component taping orientation for 44-pin plcc devices user direction of feed standard reel component orientation for 713 suffix device note: drawing does not represent total number of pins. w p package carrier width (w) pitch (p) part per full reel reel size 44-pin plcc 32 mm 24 mm 500 13 in carrier tape, number of components per reel and reel size
? 2002-2012 microchip technology inc. ds21456d-page 27 tc7109/a 7.0 revision history revision d (december 2012) added a note to each package outline drawing.
tc7109/a ds21456d-page 28 ? 2002-2012 microchip technology inc.
? 2002-2012 microchip technology inc. ds21456d-page 29 tc7109/a the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
tc7109/a ds21456d-page 30 ? 2002-2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21456d tc7109/a 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2002-2012 microchip technology inc. ds21456d-page 31 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2002-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620768358 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
ds21456d-page 32 ? 2002-2012 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/29/12

▲Up To Search▲

Price & Availability of TC7109CKW

	To Download TC7109CKW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .